`timescale 10ns/1ns
module counter_test;
  reg clk,reset;
  wire[3:0] out;
  counter_28 u1(out,reset,clk);
  initial
  begin
    clk=0;
    reset=1;
    #10 reset=0;
  end
  always #5 clk=~clk;
  initial $monitor($time, , ,"out=%b reset=%b clk=%b",out,reset,clk);
endmodule